The present invention concerns a data storage and data-processing apparatus, as well as a method for fabricating the same.
The invention particularly concerns a data storage and data-processing apparatus 3D scalable single- and multilayer memory and data-processing modules and apparatus; and which even more particularly are based on ROM and/or WORM and/or REWRITABLE blocks addressed in a passive matrix scheme.
The present application claims priority from Norwegian Patent Application No. 982518 titled xe2x80x9cScalable integrated data-processing devicexe2x80x9d, which has been assigned to the Assignee of the present invention and the disclosure of which is hereby additionally incorporated by reference. This scalable integrated data-processing device, particularly a microcomputer, comprises a processing unit with one or more processors and a storage unit with one or more memories. The data-processing device is provided on a carrier substrate and comprises mutually adjacent, substantially parallel layers stacked upon each other. The processing unit and the storage unit are each provided in one or more such layers and/or in layers formed with a selected number of processors and memories in selected combinations.
In each layer are provided horizontal electrical conducting structures which constitute internal electrical connections in the layer and besides each layer comprises further electrical conducting structures which provide electrical connections to other layers and to the exterior of the data processing device. These further electrical structures in a layer are provided on at least a side edge of the layer as electrical edge connections and/or preferably as vertical conducting structures which form an electrical connection in a cross-direction of the layer and perpendicular to its plane to contact electrical conducting structures in other layers.
In particular, the layers may be formed of a plurality of sublayers made of organic thin-film materials. Some of all layers or sublayers may also be made with organic or inorganic thin-film materials or both.
A preferred embodiment of the data-processing device according to the priority application is shown in FIG. 1. Advantageously are here processors and memories, the latter, e.g., RAMs assigned to the processors, provided in one and the same layer. A processor interface 3 with an I/O interface 8 is provided on a substrate S and above the processor interface 3 follows a processor layer P1 with one or more processors. Both the processor interface 3 and the processor layer P1 may as the lowermost layers in the data-processing device and adjacent to the substrate be realized in conventional, e.g., silicon-based technologies.
Above the processor layer P1 is provided a first memory layer M1 which may be configured with one or more RAMs 6 assigned to the processors 5 in the underlying processor layer P1. In FIG. 1, however, the separate RAMs 6 in the memory layer M1 are emphasized in particular. On the other hand it is shown how the memories in the memory layer M1 may be directly connected to the underlying processor layer P1 via buses 7, the stacked configuration allowing such buses 7 to be provided in a large number by being realized as vertical conducting structures, while the configuration layer-on-layer allows for a large number of such bus connections being provided between the processor layer P1 and the memory layer M1 and in addition with short signal paths. It will be realized that the juxtaposed arrangement in a surface would in contrast require longer connections and consequently longer transfer times.
Further, the data-processing device as shown comprises combined memory and processor layers MP1, MP2, MP3 provided with processors that are connected mutually and to the processor interface 3 via the same processor bus 4. All the combines memory and processor layers MP comprises one or more processors 5 and one or more RAMs 6. Above the combined memory and processor layers MP there is provided a memory interface 1 with an I/O interface 9 to external units and above the memory interface 1 follows memory layers M2, M3, . . . in as large number as desirable and possibly realized as the mass memory of the data-processing device. These memory layers, M2, M3, etc. are in their turn connected to the memory interface 1 via memory buses realized as vertical conducting structures 2 through the layers M2, M3, . . . .
The integrated data-processing device has a scalable architecture, such that, in principle, the device can be configured with an almost unlimited processor and memory capacity. In particular, the data-processing device can be implemented in various forms of scalable parallel architectures integrated with optimal interconnectivity in three dimensions.
In addition to comprising random accessible memories, the storage unit of the data-processing device can also comprise memories in the form of ROM, WORM or REWRITEABLE or combinations thereof.
The present invention particularly discloses how the three-dimensional scalable single- and multilayer memory and data-processing modules may be implemented with architectures and processing methods making them suitable for application in a scalable integrated data-processing device of the above-mentioned kind, but not necessarily limited thereto.
Advanced DRAM demonstration dies are presently available in 1-gigabit (Gbit) modules based on a 0.18 xcexcm process over a 570 mm2 chip area. The conventional one-transistor DRAM cell requires roughly 10xcex2 area (where xcex is the minimum feature size) although processing xe2x80x9ctricksxe2x80x9d can reduce this significantly (40%). However row and column decode, drivers, sense amplifiers, and error correction logic cannot share the same silicon area and account for a significant fraction of the DRAM die area. More importantly, existing DRAM designs to date have not proven scalable to a 3D stacked architecture. By their design, high density DRAM""s are also inappropriate as ROM memories. The conventional NOR-gate based ROM requires a nominal cell of 70xcex2 (though again reduced by processing tricks) limiting densities to  less than 108 bits/cm2 under even the most aggressive lithography assumptions. Higher densities can only be achieved through the use of both dense metal designs (minimum metal pitch) coupled with 3D integration. Technically and commercially viable devices of this type have as yet not been forthcoming, although the enormous commercial potential has prompted a great deal of RandD efforts by the electronics industry, which in term has spawned a voluminous patent literature.
3D Data Storage
Stacking of thin layers of memory on top of each other to achieve high volumetric and areal densities has been attempted by using e.g. lift-off techniques for inorganic thin film circuitry. However, the background art has led to designs that have proven too complicated or costly to have a commercial impact. In U.S. Pat. No. 5,375,085 xe2x80x9cThree dimensional ferroelectric integrated circuit without insulation layer between memory layersxe2x80x9d, B. E. Gnade et al. have disclosed a layered, passively addressed memory stack based on a ferroelectric memory substance. However, no concrete information is given, in particular relating to processability in multiple levels, showing how complete memory devices can be made that include all the required ancillary active circuitry. Several patent applications involving stacking of thin film memory layers etc. and which are of relevance for the present invention, have been filed by the present applicant. These include Norwegian patent applications NO 973993, NO 980781, the above-mentioned NO 982518, NO 980602 and NO 990867.
Dense Metal Designs
Passive matrix addressing provides a density corresponding to a unit cell area of approximately 4xcex2.
A number of patents exist where ROM devices employ passive matrix addressing schemes, e.g.: U.S. Pat. No. 4,099,260 of D. N. Lynes et al.: xe2x80x9cBipolar read-only-memory unit having self-isolating bit-linesxe2x80x9d; U.S. Pat. No. 4,400,713 of K. G. Bauge and P. B. Mollier: xe2x80x9cMatrix array of semiconducting elementsxe2x80x9d; U.S. Pat. No. 5,170,227 of M. Kaneko and K. Noguchi: xe2x80x9cMask ROM having monocrystalline silicon conductorsxe2x80x9d; U.S. Pat. No. 5,464,989 of S. Mori et al.: xe2x80x9cMask ROM using tunnel current detection to store data and a method of manufacturing thereofxe2x80x9d; U.S. Pat. No. 5,811,337 by J. Wen: xe2x80x9cMethod of fabricating a semiconductor read-only memory device for permanent storage of multilevel coded dataxe2x80x9d and PCT Pat. WO 96/41381 of F. Gonzalez et al.: xe2x80x9cA stack/trench diode for use with a multistate material in a non-volatile memory cellxe2x80x9d. However, such schemes rely explicitly on traditional silicon wafer processing, involving e.g. thermal treatment, implantation and etching procedures which are incompatible with the goals of the present invention, i.e.: low cost and optionally multilevel data storage.
The above-mentioned cited U.S. Pat. No. 5,375,085 discloses devices based on passive matrix addressing, but restricted to the special case of ferroelectric memory materials. The ferroelectric materials referred as examples in that patent have, however, proven unsuitable in simple passive matrix addressed memory schemes due to loss of polarization in unselected cells subjected to repeated partial switching. One- and two-transistor ferroelectric RAM (FERAM) devices avoid this problem, but have not lent themselves to simple 3D scaling.
In U.S. Pat. No. 5,441,907 xe2x80x9cProcess for manufacturing a plug-diode mask ROMxe2x80x9d, H-C. Sung and L. Chen discloses a passive matrix addressed ROM where binary data are coded at each matrix crossing point by the presence or absence of a diode connection. However, methods describing fabrication of devices according to the referred patent involve several high temperature steps, include final annealing, which precludes construction of multilayers and the use of low-cost, low temperature compatible materials.
Thin Film ROM Devices
In GB Patent 2,066.566 xe2x80x9cAmorphous diode and ROM or EEPROM device utilizing samexe2x80x9d, S. H. Holmberg and R. A. Flasck discloses thin film memory devices based on fluorine-containing amorphous silicon. In U.S. Pat. No. 5,272,370 xe2x80x9cThin-film ROM devices and their manufacturexe2x80x9d, I. D. French discloses a ROM device based on thin-film memory cells in a passive matrix addressing arrangement. Emphasis is explicitly on multilevel (i.e. multi-bit) data storage in each memory cell, by providing multilayer structures that can be individually selected for each memory cell.
It is a main object of the present invention to provide architectures and technical solutions where dense bit cell patterns in 2D can be incorporated into 3D storage structures, employing easily implementable, low-cost manufacturing technologies.
It is a further object of the present invention to provide ROM, WORM, and REWRITABLE memory devices with short random access times, high data transfer rates and low power consumption. In the present document, the term xe2x80x9cREWRITABLExe2x80x9d shall be used in connection with memory cells where information that has been stored can be exchanged by new information through an erase/write or direct overwrite operation. Depending on the application, this operation may be performed only once, or repeatedly.
It is yet a further object of the present invention to provide integrated data storage and processing devices where memory structures and device architectures can be created in very dense structures characterized by short, highly parallelized interconnection paths in two and three dimensions.
Finally, it is also an object of the invention to provide a fabrication method for a data storage and data-processing apparatus based on low-temperature compatible processes and materials suited therefor.
The above-mentioned objects and advantages are realized by one or more embodiments of the present invention. The objects of the present invention are particularly achieved by exploiting novel materials and processes that make possible the creation of devices with new architectures in two and three dimensions. Salient features in that connection are:
1) Memory modules are made by low-temperature compatible processes and materials i.e. polymers or low temperature processing of poly- or micro- or amorphous silicon. Low-temperature compatible in this context refers to processes not exceeding static temperatures compatible with polymer-like substrates, or transient heating processes limited to times sufficiently short to be similarly compatible. As an example: In laser crystallization of thin film silicon, the temperature in the outermost layer is in fact quite high, but due to the short thermal pulse and total energy density, heat redistributes quickly into supporting layers. Beyond a certain depth, the latter do not reach high temperatures due to calorimetric effects. For simplicity, low temperature compatible processes and materials as described above may be referred to in the following as xe2x80x9clow temperature processingxe2x80x9d and xe2x80x9clow temperature materialsxe2x80x9d.
2) Low temperature processing makes possible the creation of memory modules in one superlayer or a stack of superlayers without damaging underlying circuitry nor other memory layers in the stack. This applies both to devices based on traditional single crystal silicon substrates, as well as plastic substrates with thin-film active circuitry. (In the latter case, the short duration of the heat pulse typically used in laser recrystallization appears to prevent damage to the plastic even at temperatures where a sustained thermal load would cause damage).
3) From 1) and 2) follow a number of beneficial consequences:
Possibility of stacked layers. Leads to:
High volumetric data density, and:
High density, short vertical interconnects, leading to high data throughput:
Low capacitive and resistive interconnects due to short distance
high degree of parallelism (many vertical connections) for large word widths.
Exploiting areas in sublayer single crystal or high performance polycrystalline, amorphous or microcrystalline layer underneath memory modules for tasks requiring high-speed active circuitry. Examples:
Integrated SRAM data cache
Driver and interface electronics
On-board error detection and correction block-oriented circuitry to increase reliability of memory layers
High area data density in each layer due to the passive matrix addressing, with the option of locating driver circuitry layers below and/or above as well as in the same layer.
Vertical interconnections can take many forms: One is penetrating conductors through vias, in which case the short distances and large areas available in the stacked concept permit high data transfer speeds as mentioned above as well as flexible architectures, involving, e.g. staggered arrangement of vias as described in more detail in connection with a preferred embodiment below. Vertical interconnections can also be achieved by electrical conductors in each layer leading to the edge of the layer in question, where they are exposed and can be electrically connected to similarly exposed conductors in other layers. This may e.g. be facilitated by a step-wise extension of the edges of the lower-lying layers. Another class of vertical interconnections relies on contact-less (non-galvanic) communication through the layers. This is possible due to the layered architectures, i.e. capacitive, inductive or optical coupling between circuits in different layers.
A preferred design according to the invention is realized as a layered structure built on a single crystal silicon substrate which contains all active electronic circuitry. The latter communicates with one or more overlying memory layers through vias. Each memory layer contains low-temperature processed diode ROM and/or WORM and/or REWRITABLE arrays where high areal bit density is achieved through the use of passive matrix addressing. Each memory layer constitutes a self-contained entity and requires no high-temperature or chemically aggressive processing that can damage the underlying structures during manufacture. Thus, the memory modules can be positioned on top of active electronic circuitry in the substrate, conserving substrate real estate and providing short electronic pathways between the active circuitry and the memory modules. Furthermore, memory capacity can be expanded by adding more memory layers on top of the first, leading to a 3D stacked structure with very high volumetric bit density.
Devices as described above lend themselves well to xe2x80x9cback-endxe2x80x9d processing of the memory modules, where all circuitry on the single crystal silicon substrate is first prepared using traditional silicon foundry processing. The subsequent deposition of the memory layer(s) may be performed in a separate facility, e.g. if it is desirable to employ materials and processes in this step which might represent a contamination problem for the silicon processing.
The driver and sense circuits are preferably fabricated in a standard CMOS process on single crystal silicon substrate to minimize costs and to achieve required high data transfer rates. The ROM/WORM/REWRITABLE arrays are then built above the final metallization layer coupled by vias to the underlying drivers. The diodes can be inorganic, e.g. amorphous, polycrystalline or microcrystalline silicon, or they can be based on an organic material such as a conjugated polymer or oligomer. The passive matrix addressing scheme and the 3D architecture employing the low temperature diodes provide a dramatic storage enhancement over all existing ROM/WORM/REWRITABLE designs, at only marginal cost above the underlying CMOS circuit.
For clarity and concreteness, a detailed description of the invention shall be given below in terms of a preferred embodiment based on low-temperature processed poly-Si diode ROM arrays in a stack with four double-layer. The design can be easily extended for WORM memories applications utilizing either induced explosive crystallization of amorphous diodes or conductance modulation of interlayer organic films, and to REWRITABLE memories by incorporating highly functional memory materials in the memory matrices; cf. other patent applications belonging to the present applicant, quoted in the present document.